Description
For this project I had to layout and characterize a D Flip Flop using Cadence. This project was similar to the Standard Cell Layout project except the complexity of the layout was must high. For simple cells in a standard library there is more than enough space to position the transistors as there is only a few. In contrast the flip flop uses 24 transistors. The idea behind the standard library is to aid in the layout of complex digital designs. This means that certain constraints are imposed on the small cells.
Requirements
The requirements for the D Flip Flop were:
- An input clock slew rate of 10ps
- 0.12um supply and ground rail
- Rail to rail separation of 1.71um
- Total cell height of 1.9um
- Inputs: D, Clk, Reset (sync or async)
- Outputs: Q
