Description
The purpose of this project was to design and simulate a two-stage operational amplifier. The circuit diagram shows the topology that was used for the design. The opamp consists of 3 stages: the bias stage, the differential input stage, and the common source amplification stage. The design uses a 0.35um CMOS process. I used Cadence to simulate and test my design.
The requirements for the design are shown in table 1 alongside the actual performance that I was able to achieve in simulation with my design. The performance of the opamp was tested by simulating the differential frequency response, the closed loop frequency response, and the transient response.
