Brad MacNeil
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Soft Core Processor
Thu, 03 May 2018 13:37
FPGA
Verilog
GitHub
Requirements
Address: 32bit
Data: 32bit, integer
Math: Add, subtract, multiply, divide
Logic: And, or, not, nand, nor, exor, exnor
Bit Op: shift, rotate
Instruction Set: RISC
Language: Assembly, possibly C
Architecture: Modified Harvard