Description
The goal for this project was to create a standard library of logic cells that could be used to layout larger design components. The library consists of 3 cells; an Inverter, a 2 input NAND, and a 2 input NOR. These are all the cells that are needed to build up any digital logic cell.
Requirements
The requirements on the library were:
- An input clock slew rate of 10ps
- 0.12um supply and ground rail
- Rail to rail separation of 1.71um
- Total cell height of 1.9um
- An added challenge was minimizing both the area and the propagation delay of the cell. Finding right balance was tricky as the two are inversely related.
I used Cadence to design, layout, and test the cells . This was a real privilege because Cadence is an expensive tool and pretty tricky to get your hands on if you are not in the industry. I ended up using Cadence is a few courses and I started to enjoy using it despite barely scratching the surface of what it can do.
